Asic Development Agreement

CERTAIN INFORMATION IN THIS EXHIBIT HAS BEEN OMITTED AND FILED SEPARATELY WITH THE COMMISSION. CONFIDENTIAL TREATMENT HAS BEEN REQUESTED WITH RESPECT TO THE OMITTED PORTIONS.


Exhibit 10.15


ASIC DEVELOPMENT AGREEMENT


This is an agreement, dated as of June 24th, 1997 ("Effective Date") by and between SUPERTEC ELECTRONICS Ltd., located at 1 Hamasger St., Raanara 43653, POB 2550 Israel (hereinafter "SUPERTEC"), and NOGATECH Ltd., located at 3 Miviz Kudash St. Givat Shmuel 54100, Israel (hereinafter "CUSTOMER").


Whereas, CUSTOMER requires a design for a particular semiconductor product in accordance with the design based on LG SEMICON'S technology.


Whereas, SUPERTEC has expertise in the design of semiconductor products and believes it can perform the obligations described herein relating to the design and production of the Product in accordance with this Agreement; and


Whereas, LG SEMICON has expertise in the manufacturing of integrated circuits, and believes it can perform the obligations described herein relating to the production of a design for Product and the manufacture of the Product in accordance with this Agreement;


Whereas, CUSTOMER desires to purchase from SUPERTEC as its sole supplier for the following design, and targeting for the quantity of more than 1 MILLION units per year and SUPERTEC desires to sell such semiconductor products which are developed by CUSTOMER and SUPERTEC and produced by LG SEMICON.


Now, therefore, in consideration of the Agreements between SUPERTEC and LG SEMICON the parties hereto agree as follows:


PRODUCTION & DEVELOPMENT


SUPERTEC and CUSTOMER agree to use their respective best efforts to perform the Design Steps for which such party is responsible as follows and to complete each such Design Step by the appropriate Target Completion Date as follows:


1. DEFINITION


Project Name: NT 1003
Part Number: GVS 853XX
Package: 100 PQFP
Technology: 0.35 um SC TLM
Size: 4,014 um x 4,014 um
Description: 80 K gate 4 K byte DPRAM, USB transceiver, PLL,
Power-On-Reset, Clock Generator


2. DEVELOPMENT OF PRODUCT


2.1 Development of * module (DRAM controller preliminary estimation *-*
******). 2.2 Synthesis of RTL Varilog files and test vectors generation (preliminary
satisfaction - * ****** of **** time of an engineer). 3.3 Development of ***** ***** ASIC in *.* um SC for ****** fair (including **
K gate, * K byte DPRAM, *** transceiver). 2.4 Development of second stage **** ASIC in *.** um S.C.


* If there is a significant change in the development hours (more than 10%)
SuperTec should notified Nogatech to get the exceeded hours.


3. FORECAST FOR COMPLETION DATES


Design Step Completion Date
----------- --------------- * Beginning of ASIC design Upon placement of the CUSTOMER'S order * Design1 module 1-2 months - by Supertec * Altera preliminary NL + TV Beginning of July - Nogatech releases * Altera Full Integration Aug 3rd - Nogatech releases * Altera Final NL + TV Aug. 10th - Nogatech releases * LG final NG + TV Aug. 24th - Supertec releases * LG final NG + TV tape-out Sep. 1st - Nogatech approval * 1st Sign-Off, (*.*um) Sep. 8th - Nogatech approval * SDF out (*.*um) Sep. 15th - LG releases * 2nd Sign-Off (*.*um) Sep. 18th - Nogatech approval * Delivery of Prototypes (*.*um) Oct. 20th - by LG ex Korea * LG NI + TV tape-out (*.**um) Nov. 6th - by LG ex Korea * 1st Sign-Off, (*.**um) Nov. 10th - Nogatech approval * SDF est (*.**um) Nov. 17th - LG releases * 2nd Sign-Off.(*.**um) Nov. 20th - Nogatech approval * Delivery of Prototypes (*.**um) Dec. 25th - by LG ex Korea * Prototype Approval (*.**um) Jan 8th 1998- Nogatech approval * Mass Production (*.**um) Feb. 26th 1998 - by LG ex Korea


[**] CERTAIN INFORMATION IN THIS EXHIBIT HAS BEEN OMITTED AND FILED SEPARATELY WITH THE COMMISSION ...