Form of Wafer Supply Agreement BY And Between Amd And The Foundry Company

Exhibit 10.1

WAFER SUPPLY AGREEMENT

This WAFER SUPPLY AGREEMENT (this " Agreement" ) is made this [____] day of [__________], 200[_], (the " Effective Date" ), by and among (i) Advanced Micro Devices, Inc . , a Delaware corporation (" AMD" ); (ii) with respect to all of the provisions in this Agreement other than those in Sections 5.5(a), 6.2 and 7.3(a) and the related provisions in connection with U.S. sales activities only (though without limiting FoundryCo' s guarantee obligations pursuant to Section 15.7), [FoundryCo], an exempted company incorporated under the laws of the Cayman Islands (" FoundryCo" ) on behalf of itself and its direct and indirect wholly-owned subsidiaries, including all FoundryCo Sales Entities and FoundryCo Manufacturing Entities, as further set forth herein; and (iii) subject to FoundryCo' s guarantee obligations pursuant to Section 15.7, with respect to Sections 5.5(a), 6.2 and 7.3(a) and the related provisions in connection with U.S. sales activities only, [USOpCo], a [Delaware] corporation and a wholly-owned subsidiary of FoundryCo (" USOpCo" ). WHEREAS, AMD has been in the business of designing and manufacturing semiconductor products; WHEREAS, AMD desires to transfer its business of manufacturing and sorting semiconductor products to FoundryCo pursuant to the Master Transaction Agreement by and among AMD, Advanced Technology Investment Company LLC and West Coast Hitech L.P., dated as of October 6, 2008 (as may be amended from time to time, the " Master Agreement" ); WHEREAS, it is the intent of the parties that this Agreement establish a productive, mutually-beneficial relationship among the parties that will mitigate key risks for each party by establishing volume, capacity and pricing commitments by each party pursuant to the terms and conditions set forth herein;

WHEREAS, the parties also desire that this Agreement help establish business processes for the parties to work closely together on planning capacity and supply; WHEREAS, FoundryCo is a company whose primary purpose is the provision of wafer fabrication foundry services and FoundryCo is willing to provide such services to AMD on the terms and conditions set forth herein, and AMD is willing to engage FoundryCo to provide foundry services to AMD on the terms and conditions set forth herein; and WHEREAS, all purchases of Products by AMD will be made from FoundryCo Sales Entities, including USOpCo, and all manufacturing of Products for AMD will be made by FoundryCo Manufacturing Entities;

NOW, THEREFORE, in consideration of the mutual promises of the parties, and of good and valuable consideration, it is agreed by and among the parties as follows:

1. DEFINITIONS For the purpose of this Agreement the following capitalized terms are defined in this Section 1 and shall have the meaning specified herein. Other terms that are capitalized but not specifically defined below or in this Agreement shall have the meaning set forth in the Master Agreement.

1.1 " Actual Quarterly GPU Wafers Shipped" shall mean the actual number of Wafer Outs for GPU Products delivered in a fiscal quarter from the applicable FoundryCo Sales Entities to AMD.

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.2 " Actual Quarterly Total GPU Wafer Demand" shall mean the actual number of Wafer Outs for GPU Products delivered in a fiscal quarter from all foundry partners to AMD.

1.3 " Actual Quarterly GPU Wafer Demand Percentage" is calculated as Actual Quarterly GPU Wafers Shipped divided by Actual Quarterly Total GPU Wafer Demand.

1.4 " AMD Furnished Property" shall mean materials or tooling that AMD consigns to the applicable FoundryCo Manufacturing Entities for use by the applicable FoundryCo Manufacturing Entities to process AMD' s Product orders or to perform services on AMD' s behalf, as further set forth in this Agreement, including such materials or tooling (other than Sort Equipment owned by the applicable FoundryCo Manufacturing Entities on the Effective Date pursuant to the Master Agreement) required by the FoundryCo Manufacturing Entities to provide Sort Services pursuant to the terms of this Agreement.

1.5 " AMD Indemnified Parties" shall have the meaning set forth in Section 10.2.

1.6 " AMD MPU Specific Development Wafer Cost" shall mean the sum of:

(a) During a Period, the number of Development Wafer Starts for MPU Products multiplied by the AMD MPU Specific Direct Material Cost, divided by the sum of the number of Production Wafer Starts for MPU Products and the number of Development Wafer Starts of MPU Products, which, in an equation format, shall be:

(

Development Wafer Starts

for MPU Products )( AMD MPU Specific Direct Material Cost ) ; and

( Production Wafer Starts for MPU Products ) + ( Development Wafer Starts for MPU Products )

(b) During such Period, (i)(1) the number of Development Wafer Starts for MPU Products multiplied by the Development Factor and then multiplied by (2) the AMD MPU Specific Manufacturing Costs less the AMD MPU Specific Direct Material Cost, divided by (ii) the sum of (1) the number of Production Wafer Starts for MPU Products and (2) the number of Development Wafer Starts for MPU Products multiplied by the Development Factor, which, in an equation format, shall be:

(

Development Wafer Starts for MPU Products )(

Development

Factor )(

AMD MPU Specific Manufacturing Cost AMD MPU Specific Direct Material Cost )

(

Production Wafer Starts

for MPU Products ) + (

Development Wafer Starts

for MPU Products )(

Development

Factor )

1.7 " AMD MPU Specific Direct Material Cost" shall mean the actual cost of Raw Wafers for MPU Products.

1.8 " AMD MPU Specific Fixed Cost" shall mean all AMD MPU Specific [****] actually incurred during a Period, other than the AMD MPU Specific [****]. For the avoidance of doubt and notwithstanding anything to the contrary, AMD MPU Specific Fixed Cost shall include, and AMD shall pay, [****] for the [****] existing on the Effective Date (which shall be [****] in [****] and [****] in [****]) and [****] for the [****] to be put in [****] to [****] AMD MPU Product [****], and agreed to by the parties, pursuant to Sections 2.2 and 5.1 that have not been recouped by the applicable FoundryCo Manufacturing Entities.


[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.9 " AMD MPU Specific Inventory Change" shall mean the amount calculated by subtracting (a) the gross inventory dollars attributable to MPU Products manufactured for AMD at the end of a relevant Period from (b) the gross inventory dollars attributable to MPU Products manufactured for AMD at the beginning of such Period (excluding, in each case, Raw Wafers).

1.10 " AMD MPU Specific Manufacturing Costs" shall mean all [****] and [****] costs incurred in the MPU Product wafer manufacturing process (including [****] Services Cost and [****] cost (which shall include [****] on [****] owned by the FoundryCo Manufacturing Entities on the Effective Date), and whether or not such wafers are [****] and whether or not such wafers are [****] or are in [****]) and which would properly be included according to industry and accounting standards in the cost of a [****], [****] or a [****]. AMD MPU Specific Manufacturing Costs shall not include [****], nor shall it include [****] or [****] and [****]. AMD MPU Specific Manufacturing Costs shall be equal to the sum of AMD MPU Specific [****] and AMD MPU Specific [****]. In addition, AMD MPU Specific Manufacturing Costs shall be equal to the sum of AMD MPU Specific [****] and AMD MPU Specific [****].

1.11 " AMD MPU Specific Other COGS" shall mean FoundryCo' s allocation of other costs of goods sold related to MPU Products not otherwise specified as AMD MPU Specific [****], as determined in accordance with industry and accounting standards as generally applied by FoundryCo, and which includes as of the Effective Date a portion of the [****] of [****] related [****], a portion of the [****] of the [****] organization (mostly within the sub-organization [" ****," ] which is almost entirely [****]), a portion of the [****] related to [****], as well as a portion of other costs (including certain [****] allocated to COGS) that are incurred in direct support of the [****] in the FoundryCo Manufacturing Entities' facilities.

1.12 " AMD MPU Specific Production Wafer Cost" shall mean the sum of: (a) During a Period, the number of Production Wafer Starts for MPU Products multiplied by the actual AMD MPU Specific Direct Material Cost, divided by the sum of the number of [Production Wafer Starts for MPU Products and the number of Development Wafer Starts for MPU Products, which, in an equation format, shall be: (

Production Wafer Starts

for MPU Products )( AMD MPU Specific Direct Material Cost )

( Production Wafer Starts for MPU Products ) + ( Development Wafer Starts for MPU Products )

; and

(b) During such Period, (i)(1) the number of Production Wafer Starts for MPU Products multiplied by (2) the AMD MPU Specific Manufacturing Costs less the AMD MPU Specific Direct Material Cost, divided by (ii) the sum of (1) the number of Production Wafer Starts for MPU Products and (2) the number of Development Wafer Starts for AMD MPU Products multiplied by the Development Factor, which, in an equation format, shall be:

(

Production Wafer Starts

for MPU Products ) (

AMD MPU Specific Manufacturing Cost AMD MPU Specific Direct Material Cost )

(

Production Wafer Starts for MPU Products ) + (

Development Wafer Starts for MPU Products )(

Development

Factor )

1.13 " AMD MPU Specific Total COGS" shall mean the sum of AMD MPU Specific Production Wafer Cost, AMD MPU Specific Other COGS and AMD MPU Specific Inventory Change.


[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.14 " AMD MPU Specific Variable Cost" shall mean those AMD MPU Specific Manufacturing Costs actually incurred during a Period, consisting of AMD MPU Specific Direct Materials Cost, and [****] percent ([****]%) of [****].

1.15 " AMD-Specific Engineering Expense Allocation" shall mean the actual costs incurred by FoundryCo Manufacturing Entities in developing AMD-Specific Manufacturing Process Technologies.

1.16 " AMD-Specific License Fee Allocation" shall mean [****] percent ([****]%) of the aggregate [****] fees incurred by FoundryCo according to the [****] and [****] between [****] and AMD dated as of [****], as may be amended from time to time, for both [****] and [****] process technologies, and [****] percent ([****]%) of any additional licenses required specifically for MPU Products.

1.17 " AMD-Specific Manufacturing Process Technology" shall refer to any manufacturing or sorting process technology used at the time of development by any FoundryCo Manufacturing Entity specifically for AMD. For purposes of example only, as of the Effective Date, the [****] is currently considered an AMD-Specific Manufacturing Process Technology. For the avoidance of doubt, [****] process technology, unless specifically designed to manufacture only Products, is not an AMD-Specific Manufacturing Process Technology. 1.18 " AMD-Specific Process Engineering Wafer Starts" shall mean the Wafer Starts of AMD-Specific Process Engineering Wafers.

1.19 " AMD-Specific Process Development Wafers" or " AMD-Specific Process Engineering Wafers" shall mean Process Engineering Wafers processed by a FoundryCo Manufacturing Entity utilizing an AMD-Specific Manufacturing Process Technology.

1.20 " AMD-Specific Process Engineering Wafer Cost" shall mean the portion of AMD MPU Specific Development Wafer Costs incurred to produce AMD-Specific Process Engineering Wafers. It shall be determined based on the ratio of AMD-Specific Process Engineering Wafer Starts] to Development Wafer Starts (for MPU Products).

1.21 " AMD-Specific Product Qualification Plan" shall mean the qualification tests and schedules to be agreed upon by the parties under which a Product is Qualified.

1.22 " AMD-Specific Qualification Plan" shall mean the qualification tests and schedules to be agreed upon by the parties under which an AMD-Specific Qualified Process is established and tested at the applicable FoundryCo Manufacturing Entity and the MPU Products are manufactured using an AMD-Specific Qualified Process to meet the Specifications.

1.23 " AMD-Specific Qualified Process" shall mean the wafer manufacturing processes used at the applicable FoundryCo Manufacturing Entity specifically for production of Wafers for AMD with respect to MPU Products, and any other FoundryCo-proprietary wafer manufacturing process approved by the parties specifically to produce MPU Products on AMD' s behalf. 1.24 " AMD-Specific R&D Costs" shall mean the sum of AMD-Specific [****], AMD-Specific [****] and AMD-Specific [****].

1.25 " [ **** ]" shall mean the [****] of the applicable FoundryCo Manufacturing Entities' [****] to [****] the [****] of (a) any [****] within the FoundryCo Manufacturing Entities and (b) any [****] to AMD.

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.26 " Binding Forecast" shall mean AMD' s MPU Product forecast for the first [****] months of any rolling [****] month MPU Product forecast as set forth in Section 5.1 and in accordance with Section 2.2. For the avoidance of doubt, a " Binding Forecast" shall not include any forecast that requires more capacity to manufacture the relevant Products than the capacity that had been agreed upon pursuant to Section 2.2.

1.27 " Binding Forecast Period" shall mean the first [****] months of any rolling [****] month MPU Product forecast.

1.28 " [ **** ]" shall have the meaning set forth in Section 2.1(b)(i).

1.29 " [ **** ] Change of Control Transaction" shall mean a transaction with or among [****] or any of its subsidiaries and any other person (other than FoundryCo) with respect to (a) a merger, consolidation, business combination or similar transaction of [****], (b) any purchase of an equity interest (including by means of a tender or exchange offer) representing an amount equal to or greater than a [****] percent ([****]%) voting or economic interest in [****], or (c) any purchase of assets, securities or ownership interests representing an amount equal to or greater than [****] percent ([****]%) of the consolidated assets of [****] and its subsidiaries taken as a whole (including stock of [****]' s subsidiaries); provided that a sale or transfer of assets that are not used to manufacture on behalf of [****] shall not be included in the calculation of assets to determine a [****] Change of Control Transaction.

1.30 " COGS" shall mean cost of goods sold in accordance with AMD' s standard practices in effect as of the Effective Date.

1.31 " Confidential Information" shall mean all proprietary or nonpublic information disclosed by one party to another party in connection with this Agreement, whether in graphic, oral, written or electronic form, directly or indirectly, which information (a) is marked as " proprietary" or " confidential" or, if disclosed orally, is designated as confidential or proprietary at the time of disclosure, or (b) provided under circumstances reasonably indicating that it constitutes confidential and proprietary information. 1.32 " Development Factor" shall mean a factor calculated once per fiscal year (within the first fiscal quarter of a year for application to that fiscal year) by FoundryCo to reflect [****] for processing [****] versus a [****] Wafer. The Development Factor is used for the [****] of AMD MPU Specific [****] for a Period into AMD MPU Specific [****] and AMD MPU Specific [****]. The Development Factor consists of a factor for [****] and a factor for [****] that are consolidated into one factor (weighted with the [****] of the respective [****] categories). The development factor for [****] reflects the higher effort due to engineering times before, during and after processing [****], e.g. creation of ERFs, writing reports, R&D-analysis, and split lots. The calculation is based on [****] via [****] for representative ERFs and on processing data of the ERFs in the manufacturing execution system (currently [****]). The development factor for [****] reflects the [****] for [****] versus a [****]. The data is collected and calculated through a software tool. Output of this software tool is per [****] per [****] versus [****] per [****] over [****]. This [****] will be weighted with the running [****] per [****]. As of the Effective Date, the Development Factor is [****]. 1.33 " Development Wafer Starts" shall mean the combined Wafer Starts of AMD-Specific Process Engineering Wafers and Product Development Wafers.

1.34 " Die" shall mean one of the semiconductor devices on a Wafer produced by FoundryCo for AMD using a Qualified Process.

1.35 " Dispute" shall have the meaning set forth in Section 15.11(b).


[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.36 " Dispute Notice" shall have the meaning set forth in Section 15.11(b).

1.37 " Embedded Products" shall mean x86-based semiconductor devices or any other device based on new architecture or architecture adopted in the future, in each case, other than MPU Products that are used in systems that have targeted applications, and which are not designed for use as central processing units for general purpose desktop, notebook, workstation, server computers or game consoles. Embedded Products shall include AMD' s Geode99 product lines.

1.38 " Engineering Change" shall mean any change to the process, materials, equipment, technology, location or any other items listed in FoundryCo' s standard specifications for which a change would affect the performance, function or reliability of the Wafers.

1.39 " Engineering Request Form" or " ERF" shall mean an engineering request form submitted by AMD to FoundryCo to carry out an experiment in a process line.

1.40 " Engineering Wafers" shall mean those Wafers required for the Qualification Plan or delivered to AMD for testing pursuant to AMD' s request. Engineering Wafers consist of Process Development Wafers and Product Development Wafers.

1.41 " Epidemic Failure" shall mean the occurrence of an average in-field failure rate of [****] percent ([****]%) or more per month of the total units for a particular Product delivered in any rolling [****] month period.

1.42 " Fab Start up Costs" shall mean the costs required by FoundryCo to establish new facilities or to convert existing facilities to new wafer sizes (e.g., from 200mm to 300mm) and any other costs which FoundryCo would otherwise include in this category.

1.43 " Forecasted GPU Wafer Demand" shall mean a non-binding, rolling [****] month forecast describing the monthly Wafer Outs expected to be placed by AMD on FoundryCo Sales Entities for GPU Products.

1.44 " Forecasted Total GPU Wafer Demand" shall mean a non-binding, rolling [****] month forecast describing the total Wafer Outs expected to be placed by AMD on all foundry partners for GPU Products. 1.45 " Forecasted GPU Wafer Demand Percentage" is calculated as Forecasted GPU Wafer Demand divided by Forecasted Total GPU Wafer Demand.

1.46 " FoundryCo Indemnified Parties" shall have the meaning set forth in Section 10.1. 1.47 " FoundryCo Manufacturing Entities" shall mean FoundryCo and any direct or indirect wholly-owned subsidiaries of FoundryCo to which FoundryCo has delegated the responsibility to manufacture Products for AMD in accordance with this Agreement.

1.48 " FoundryCo Sales Entities" shall mean USOpCo and any other direct or indirect wholly-owned subsidiaries of FoundryCo to which FoundryCo has delegated the responsibility to process purchase orders from AMD and to offer to sell and sell Products to AMD in accordance with this Agreement.

1.49 " Fusion Products" shall mean both (a) MPU Products that incorporate GPU Products and (b) GPU Products that incorporate MPU Products.


[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.50 " GAC" shall mean gases, acids and chemicals. 1.51 " G&A Expenses" shall mean standard general and administrative expenses, as calculated by FoundryCo in accordance with accounting standards as generally applied by FoundryCo.

1.52 " GPU Minimum Percentage" shall have the meaning set forth in Section 2.1(c)(ii).

1.53 " GPU Products" shall mean an integrated or discrete graphics processing unit. As an example, as of the Effective Date, GPU Products consist of integrated or discrete graphics processing unit for use in any of the following or similar products: desktop computers, notebook computers, servers, workstations or game consoles.

1.54 " Interim Relief Proceeding" shall have the meaning set forth in Section 15.11(c).

1.55 " Lead Time" shall mean the time between the date an order is accepted by a FoundryCo Sales Entity and the date the Wafers are made available for shipment by the FoundryCo Sales Entity.

1.56 " Major Change" shall mean a change to a manufacturing process that would affect the form, fit, or function of a Product of AMD or that otherwise materially affects a manufacturing process for AMD.

1.57 " Minimum Batch Size" shall mean the minimum total number of Wafers in a Process Batch for a particular Product. 1.58 " MPU Products" shall mean any of the following: (i) the x86, x86-64, and IA (Intel Architecture)-64 families of microprocessors, (ii) any existing or new microprocessors based on the x86, x86-64, and IA-64 family architecture, or any new instruction set for a processor described in clause (i) first introduced by AMD, (iii) any microprocessors based on new architecture or an architecture adopted in the future, or (iv) Fusion Products. As used in this definition, a microprocessor shall include a component that can execute computer programs and is the central processing unit controlling an electronic device.

1.59 " Other Future Products" shall mean any future integrated circuit devices designed by AMD other than GPU Products and MPU Products.

1.60 " Partnership Committee" shall have the meaning set forth in Section 3.2(a).

1.61 " Period" shall mean a fiscal month or fiscal quarter, as applicable to the specific measurement period in question.

1.62 " Process Batch" shall mean a group of wafers that are processed together as a group.

1.63 " Process Development Wafers" or " Process Engineering Wafers" shall mean Engineering Wafers produced by a FoundryCo Manufacturing Entity to enable it to design, develop, establish, test, improve and validate FoundryCo Manufacturing Entity manufacturing processes. For avoidance of doubt, Process Development Wafers or Process Engineering Wafers shall not include Engineering Wafers expressly requested by AMD, which shall be counted as Product Development Wafers.

1.64 " Process Node" shall mean a specific geometry loosely based on minimum line width at which semiconductor integrated circuit devices, and the photomasks or reticles used in the manufacture of those devices, are manufactured (e.g., a 45 nm process node). For avoidance of doubt, Process Nodes shall include half nodes (e.g., 40nm and 28nm process nodes).

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.65 " Product" shall mean an integrated circuit device incorporating AMD' s proprietary designs to be manufactured by the FoundryCo Manufacturing Entities and sold to AMD by the FoundryCo Sales Entities, including Embedded Products, GPU Products, MPU Products and Other Future Products. The Products will be provided to AMD as unprobed Wafers, probed Wafers or bumped Wafers, as specified in the applicable purchase order.

1.66 " Product Development Wafers" shall mean Engineering Wafers requested by AMD and produced by the FoundryCo Manufacturing Entities to test, evaluate and validate Product designs, including, but not limited to, design verification and engineering verification.

1.67 " Product Development Wafer Cost" shall mean the portion of AMD MPU Specific Development Wafer Cost related to Product Development Wafer Starts, determined as the ratio of Product Development Wafer Starts to Development Wafer Starts (for MPU Products). 1.68 " Product Development Wafer Starts" shall mean the Wafer Starts of Product Development Wafers. 1.69 " Production Wafers" shall mean the finished silicon wafers for the Products to be manufactured by the FoundryCo Manufacturing Entities in accordance with the applicable Specifications and using the Qualified Processes, and shall include Risk Starts.

1.70 " Production Wafer Starts" shall mean Wafer Starts for Production Wafers.

1.71 " Qualification Plan" shall mean the qualification tests and schedules to be agreed upon by the parties under which a Qualified Process is established and tested at FoundryCo Manufacturing Entities and relevant Wafers are manufactured using the Qualified Process to meet the Specifications.

1.72 " Qualification" or " Qualified" shall mean the mutual determination that the relevant Wafers meet the Specifications in accordance with the applicable Qualification Plan for a particular Product. 1.73 " Qualified Process" shall mean the wafer manufacturing processes used at FoundryCo for production of relevant Wafers, and any other FoundryCo Manufacturing Entity proprietary wafer manufacturing process approved by the parties to produce relevant Wafers.

1.74 " Quarterly Business Reviews" or " QBRs" shall mean business reviews held every fiscal quarter by the Partnership Committee or their designees as mutually agreed to by the parties. 1.75 " Quarterly Technical Reviews" or " QTRs" shall mean technical reviews held every fiscal quarter by the Partnership Committee or their designees as mutually agreed to by the parties.

1.76 " R & D" shall mean research and development.

1.77 " Raw Wafers" shall mean unprocessed or bare silicon wafers purchased by FoundryCo Manufacturing Entities and used by FoundryCo Manufacturing Entities as a substrate to enable the FoundryCo Manufacturing Entities to fabricate Wafers on behalf of AMD as set forth in this Agreement. 1.78 " Raw Wafer Cost" shall mean the actual cost to the FoundryCo Manufacturing Entities of a Raw Wafer.

[****] = Certain confidential information contained in this document, marked by brackets, has been omitted and filed separately with the Securities and Exchange Commission pursuant to Rule 24b-2 of the Securities Exchange Act of 1934, as amended. Confidential treatment has been requested with respect to the omitted portions.

1.79 " Recall" shall mean a recall, field correction, market withdrawal, stock rec ...