Limited Assembly Services Agreement

EXHIBIT 10.14


INTEL CONFIDENTIAL
------------------


INTEL/CHIPPAC LIMITED
ASSEMBLY SERVICES AGREEMENT


(Replacement Agreement for Intel Agreement No. 0995ELR001)


This Agreement ("Agreement") is entered into this 5th day of August, 1999 and shall become effective upon the Effective Date, by and between Intel Corporation ("Intel"), a Delaware corporation with its principal offices located at 2200 Mission College Boulevard, Santa Clara, California 95052, and ChipPAC Limited, a British Virgin Islands corporation with principal offices located at Craigmuir Chambers, Road Town, Tortola, British Virgin Islands ("ChipPAC"). Intel and ChipPAC are sometimes collectively referred to as the "Parties" or singularly as a "Party". "Effective Date" means the date of consummation of the transactions contemplated by that certain Agreement and Plan of Recapitalization and Merger dated as of March 13, 1999, as amended, by and among Hyundai Electronics Industries Company, Ltd., Hyundai Electronics America, ChipPAC, Inc. and ChipPAC Merger Corp.


RECITALS: --------


WHEREAS, Intel desires to enter into a contract assembly and test arrangement with ChipPAC as more specifically described herein.


WHEREAS, ChipPAC is in the business of doing contract assembly and test work for integrated circuit manufacturers and desires to perform such services for Intel.


WHEREAS, the Parties desire to set forth below the conditions and covenants under which such work shall be performed.


NOW THEREFORE, in consideration of the mutual covenants herein contained, the Parties agree as follows:


1. DEFINITIONS
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1.1 "[redacted*]" shall mean Intel's chipset products utilizing the
[redacted*] packaging process.


1.2 "[redacted*]" shall mean Intel's chipset products utilizing the
[redacted*] packaging process.


1.3 "[redacted*]" shall mean the chipset products utilizing the
[redacted] packaging process.


*Confidential treatment requested.


-1-


1.4 "Die Product" shall mean an Intel Product in an unassembled form,
without packaging, specified in Exhibit D, and provided by Intel to
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ChipPAC under this Agreement in order for ChipPAC to perform the
Services.


1.5 "Die Product Specification" shall mean the technical information for
each Intel Product which ChipPAC is authorized to handle under this
Agreement.


1.6 "Facility" shall mean the Intel work area in the factory provided by
ChipPAC to perform the Services as defined below.


1.7 "Intel Product" shall mean the finished product which is sold by Intel
in a packaged form and which contains the die of the related Die
Product, and which ChipPAC processes or manufactures on behalf of
Intel which complies with the Specifications/ Performance Standards
specified in Exhibit B.
---------


1.8 "Intel Product Data Sheet" shall mean the technical information for
each Intel Product supplied by Intel to purchasers of Intel Products.


1.9 "Leadframes" shall mean the leadframes that ChipPAC shall order as
Piece Parts in anticipation of fulfilling Intel's orders for
[redacted*] and [redacted*].


1.10 "Leadtime" shall mean TPT plus transit time to Intel.


1.11 "Leadtime Procurement Period" shall mean the procurement of Piece
Parts during the Leadtime period.


1.12 "LIPAS" (Line Item Performance Against Schedule) shall mean the number
of Line Items that shipped in a given week divided by the number of
Line Items scheduled by ChipPAC to be shipped during the same week per
Intel's forecast.


1.13 "Non Data Sheet Functionality" shall mean (a) features, instructions,
operating modes, and other functions which may be contained in the
Intel Product and the Die Product but which Intel does not document
and which are not required for the Intel Product and the Die Product
to comply with the related Intel Product Data Sheet, and (b) internal
nodes and signals which are not accessible at the bond pads of the Die
Product.


1.14 "Piece Parts" shall mean all materials procured and furnished by
ChipPAC in order to perform the Services under this Agreement.


*Confidential treatment requested.


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1.15 "Rejects" shall mean the product produced by ChipPAC which do not
comply with the Specifications and Performance Standards specified in
Exhibit B, are damaged or are otherwise returned to ChipPAC or
---------
rejected by Intel.


1.16 "Release" shall mean Intel's purchase order or change order accepting
ChipPAC's offer to ship a definite quantity of Intel Products or to
provide Services to a specified schedule and pricing.


1.17 "Service(s)" shall mean the work to be performed as specified in
Exhibit A in compliance with the Specifications/Performance Standards
---------
specified in Exhibit B.
---------


1.18 "Substrates" shall mean the substrate materials that ChipPAC shall
order as Piece Parts in anticipation of fulfilling Intel's orders for
[redacted*] Products.


1.19 "Through Put Time" (TPT) shall mean the number of calendar days
required to manufacture the Intel Product, starting when the Wafers or
Die Product are released from inventory at ChipPAC and ending when the
Intel Products are shipped out of ChipPAC.


1.20 "Wafer" shall mean Intel's substrate material that contains unscribed
Die Product that have been sorted by Intel as Die Product which has
passed the sort criteria for the Intel Product ("non-inked") and Die
Product which has failed the sort criteria for the Intel Product
("inked").


1.21 "Work in Process" referred to hereinafter as "WIP".


2. STATEMENT OF WORK
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2.1 ChipPAC will provide all facilities, equipment, material, manpower and
expertise necessary to perform the Services according to Intel
requirements and specifications as referenced in Exhibits A and B.
----------------


2.2 Intel shall supply ChipPAC with all Wafers and Die Product.


2.3 ChipPAC shall provide at ChipPAC's expense all Piece Parts, supplies
and peripheral products, including leadframes, required for ChipPAC to
perform the Services.


2.4 ChipPAC shall perform the Services in accordance with Intel's
requirements and specifications as specified in Exhibits A and B.
----------------


2.5 ChipPAC shall at least meet the minimum yields and maximum TPT
specified in Exhibit C, with a goal of continually improving both
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yield and TPT.


*Confidential treatment requested.


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2.6 ChipPAC shall adhere to Intel's procedures with respect to security,
traceability and accountability as specified herein.


3. PRE-PRODUCTION
--------------


3.1 In the event that Intel determines a need to have certain Intel
Products produced by ChipPAC on a limited scale or as prototypes in
order to qualify those Intel Products or the process involved or to
produce samples of the Intel Products ("Pre-Production Parts"), prior
to beginning full production, Intel and ChipPAC shall agree on the
quantity, specifications, pricing, Leadtime and other requirements for
each such Pre-Production Part. All orders for Pre-Production Parts
must first be authorized in writing by Intel. Once Intel has
qualified and accepted the Pre-Production Parts, these may be ordered
as Intel Products under the Agreement.


3.2 If Intel cancels all or part of any order for Pre-Production Parts,
Intel shall pay for the related WIP for the canceled order, as
outlined in Exhibit E, Cancellation Liability.
---------


3.3 Intel recognizes that yields for Pre-Production Parts may be difficult
to control. If ChipPAC's build amount does not provide sufficient
quantities to provide the quantity ordered by Intel, and the
outstanding amount is less than [redacted*] of the ordered quantity,
Intel may either cancel the balance of the order without penalty, or
allow ChipPAC to provide the balance of the order at a later date, not
to exceed fourteen (14) days from the date Intel provides replacement
Die Product.


3.4 ChipPAC warrants that Pre-Production Parts shall meet design test
vectors and be free of manufacturing defects, but otherwise are
provided "AS IS".


4. OWNERSHIP
---------


4.1 All Wafers and Die Product shall be held by ChipPAC for the sole
benefit of Intel. Ownership of Wafers and Die Product shall remain
with Intel. ChipPAC acknowledges that Intel retains an ownership
interest in the Wafers and Die Product and agrees to assist Intel in
perfecting said security interest under the Uniform Commercial Code
------- ---------------
and other relevant laws, at Intel's request. Ownership of all Rejects
shall remain with Intel.


5. CONFIDENTIALITY AND PUBLICITY
-----------------------------


5.1 Any confidential information to be exchanged between the Parties shall
be governed by the terms of the Corporate Non-Disclosure Agreement
(CNDA) number 0875665, which ChipPAC agrees to be bound by. At a
minimum, ChipPAC agrees to maintain such information in confidence,
pursuant to the terms of the above-referenced CNDA,


*Confidential Treatment requested.


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to take all reasonable precautions to prevent unauthorized disclosure
and to use such information only within the scope of this Agreement
until the information becomes publicly available through no fault of
ChipPAC. Examples of confidential information include, but are not
limited to, Wafers, Die Product, Die Product Specifications, yield,
probe characteristics, number of Wafers, and number of Die Product.


5.2 ChipPAC is responsible for (i) secure storage in a segregated
Facility, handling, processing and return of Intel Product
incorporating Die Product, and (ii) the return (or certified
destruction) of all scrap/Rejects to Intel. ChipPAC will be liable
for any loss, including, but not limited to, theft, destruction, and
deterioration.


5.3 ChipPAC's Facility, manufacturing and wafer processing areas must be
secure and accessed only by ChipPAC's employees or contractors on a
need-to-know basis. Any third party, including contract employees,
involved in any aspect of Wafer or Die Product shipping, storage,
security, processing, assembly, or handling must sign a Non-Disclosure
Agreement with Intel.


5.4 ChipPAC's employees who access Intel's premises may be required to
sign a separate non-disclosure agreement prior to admittance to
Intel's premises.


5.5 ChipPAC warrants that no information disclosed by ChipPAC to Intel, in
any form whatsoever, is the confidential information of any other
party without written authorization from that Party.


5.6 Neither Party may use the other Party's name in advertisements, news
releases, publicity statements, on the internet, or otherwise disclose
the existence or content of this Agreement, without the other's prior
written consent.


6. DELIVERY, RELEASES AND SCHEDULING
---------------------------------


6.1 Intel shall provide ChipPAC with a rolling [redacted*] operating
forecast of its requirements every week. An Intel Work Week Calendar
sample is attached as Exhibit G.
---------


6.2 Response: ChipPAC shall provide a written response to Intel's
[redacted*] requirements forecast letter within seven (7) working
days after receipt. If no response is received by Intel in this time
period, then the forecast is deemed to be approved by ChipPAC.


6.3 ChipPAC shall use the forecast only as a guide to adequately prepare
for Intel's anticipated requirements. Intel is not obligated to
purchase any specific business under this Agreement. Intel's
forecasts are subject to change and are not commitments. ChipPAC
understands that Intel's demand is dependent on market and


*Confidential treatment requested.


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other factors beyond Intel's control and this may result in demand
being reduced, increased or eliminated.


6.4 ChipPAC shall meet the Intel unit requirements as set forth in the
shipping Release for the applicable purchase order as acknowledged by
ChipPAC as specified in paragraph 6.2 above.


6.5 Intel shall place with ChipPAC a Release for each Intel Product by the
minimum Leadtime required, specifying quantity, delivery date and
delivery place. ChipPAC agrees to acknowledge in writing each Release
within five (5) working days. ChipPac shall make weekly delivery
commitments by Line Item for the weekly Intel requests and monthly
delivery commitments by Line Item for the remaining months of the
forecast period. ChipPAC's delivery commitment shall be firm for the
Leadtime Procurement Period. Intel may make changes to its Releases at
any time in the form of "Demand Exceptions". Such Demand Exception
changes shall be sent immediately to ChipPAC in writing by fax or
other electronic means. ChipPAC must provide to Intel a written
response to Intel's Demand Exceptions via fax or e-mail within twenty-
four (24) hours after receipt of the Demand Exception changes. At such
time as Intel receives ChipPAC's committed response to the Demand
Exceptions, Intel shall update the Release accordingly. Leadtime
Procurement Period for [redacted*] is [redacted*] weeks.


6.6 ChipPAC agrees that all orders for Intel Products will ship on the
exact date specified. In the event that an order shipment is going to
be late, Intel must be notified as soon as ChipPAC is aware that the
Intel Product will not meet its committed ship date. Partial shipments
must be authorized by Intel and are counted as late shipments and will
only be considered complete when all Intel Products for that order
have been received. If shipments are late by more than seven (7) days,
at no fault of Intel, at Intel's option, Intel can cancel the order
with no charge. ChipPAC will be responsible for any costs incurred by
Intel in obtaining cover in the event of such order cancellation.
Intel shall have no obligation for orders shipped more than seven (7)
days late.


6.7 ChipPAC shall promptly notify Intel if ChipPAC is unable to perform
Services or deliver orders as scheduled and shall state the reasons
for such non-delivery or non performance. Such notification by
ChipPAC shall not affect Intel's termination rights.


6.8 Delivery Performance. ChipPAC's LIPAS performance shall be 100%. If
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ChipPAC's LIPAS performance falls below 100% for any reason, at no
fault of Intel, then ChipPAC shall promptly implement a corrective
action plan approved by Intel to bring LIPAS back into 100%
compliance. On-time deliveries for LIPAS performance measurement are
defined as ChipPAC shipping the Intel Product units that are due for
that week's delivery up to [redacted*] days early but [redacted*] days
late from the


*Confidential treatment requested.


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committed ship date specified on the purchase order. If ChipPAC's
delivery is [redacted*] or more days late, a [redacted*] discount
shall apply to the specific line items that are shipped late.


6.9 Intel may place any portion of a Release on hold by notice which shall
take effect immediately upon receipt. Releases placed on hold will be
rescheduled or canceled within a reasonable time (to be mutually
agreed upon by Intel and ChipPAC).


6.10 [redacted*] At a minimum, ChipPAC shall provide ship dates based on
TPT after receipt of a Release. For purposes of determining ship date
TPT, the date that a Release is sent (by fax, electronic means or
mail) will be the starting point for calculating the TPT.


6.11 Intel-requested or Intel-approved changes that result in ship date
changes will be reflected on a written change order to the Release
showing the revised ship and delivery dates.


6.12 ChipPAC shall maintain a safety stock of Piece Parts including
Leadframes and Substrates in sufficient quantity to maintain
production in accordance with the then-current Intel forecasts of four
(4) consecutive weeks for [redacted*] and [redacted*] packages and six
(6) consecutive weeks for new packages such as [redacted*] ("Safety
Stock Level"), in addition to the quantity specified on the then
current Release, unless otherwise requested by Intel in writing. Intel
shall be responsible for the cost of the Safety Stock Level for the
Leadframes and Substrates. All other Piece Part liability is covered
by paragraph 6.13 below.


6.13 Cancellation. If Intel cancels all or part of any order for Intel
------------
Products, Intel shall pay for the related WIP for the canceled order,
as outlined in Exhibit E, Cancellation Liability.
---------


6.14 Rescheduling. Intel may at any time, not later than seven (7) days.
------------
before the scheduled delivery date, reschedule any Release line item
from such scheduled delivery date to another date. Intel will be
liable only for the Piece Parts ordered relating to the specific
Release line item as outlined in Exhibit E, Cancellation Liability.
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Intel may also place all or any part of an order on hold, which shall
take place immediately upon receipt of notice by ChipPAC. Orders
placed on hold shall be canceled or rescheduled within a reasonable
time.


6.15 ChipPAC Notice. ChipPAC shall promptly notify Intel if ChipPAC is
--------------
unable to make any scheduled delivery, and shall state the reasons.


*Confidential treatment requested.


-7-


7. REPORTING
---------


7.1 ChipPAC shall provide Intel with a weekly report of all inventories
(including Die Product inventory), production schedule status, WIP
inventory, shipment, and any and all engineering and quality data
required for yield loss analysis to a designated Intel Representative
at Intel ISSL. This report must be in Intel's possession by 12:00
noon each Monday (Korean time) for the previous week. Intel may at
any time, upon one (1) business day's notice to ChipPAC, conduct a
physical inventory of all such Wafer, Die Product, Intel Products, WIP
and/or Rejects in the possession of ChipPAC.


7.2 At Intel's option, ChipPAC shall provide the Intel Program Manager,
with a soft copy or hard copy of monthly reports to a designated Intel
representative of all shipouts, ending-on-hand inventories (including
Wafer and Die Product inventory), Rejects, and units in-transit out of
production Facility to Intel. This report must be in Intel's
possession on the Intel month-end Friday by the end of the business
day (U.S. Pacific Time). Intel may at any time, upon one (1) business
day's notice to ChipPAC, cycle count and/or audit inventory all such
Wafers and Die Product, Intel Product and/or Rejects in the possession
of ChipPAC.


8. PRICE AND PAYMENT
-----------------


8.1 For the [redacted*] products there is no non-recurring engineering
("NRE") charges. For future products, the parties may negotiate NRE
charges to be paid by Intel.


8.2 Prices charged by Hyundai, ChipPAC's predecessor, for the Services
during the one-year period from September 16, 1996 are specified in


Exhibit E. The pricing schedule specified in Exhibit E shall remain
--------- ---------
firm or decline for the one-year period from September 16, 1996 unless
process changes are made by Intel, in which case a revised pricing
schedule shall be mutually agreed to by both Parties. Notwithstanding
the above, in extraordinary circumstances wherein Intel requests
changes to the Intel Product that substantially affect the price or if
market factors have changed which substantially affect the price, the
Parties will negotiate a revised pricing schedule which shall be
mutually agreed to by both Parties.


8.3 Hyundai, ChipPAC's predecessor, warranted that prices set forth in
Exhibit E reflect [redacted*] in consideration of the volume of Intel
Product purchases forcast by Intel. [redacted*] Intel and ChipPAC
agree to review the pricing under this Agreement not less than every
ninety (90) days [redacted*], and that ChipPAC is successful in
continually reducing the pricing provided to Intel.


*Confidential treatment requested.


-8-


8.4 Invoices shall include: purchase order number, description of and
dates of Services provided, prices and extended totals. Payment shall
not constitute acceptance of Intel Products. Applicable taxes and
other charges such as duties, customs, tariffs, imposts and government
imposed surcharges shall be stated separately on ChipPAC's invoice.


8.5 Additional costs, beyond those described on Exhibit E, shall not be
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reimbursed without Intel's prior written approval.


8.6 ChipPAC shall provide invoices with each shipment to Intel. All such
invoices shall be paid by Intel in U.S. dollars, net thirty (30) days
from the receipt of an acceptable invoice. The invoice amounts shall
be calculated based on the pricing set forth in Exhibit E or such
---------
other pricing mutually agreed upon by Intel and ChipPAC.


9. QUALITY AND RELIABILITY
-----------------------


9.1 Qualification Requirements. ChipPAC is responsible for meeting and
--------------------------
maintaining Intel's Quality and Reliability (Q&R) requirements as
listed in the Specifications referenced in Exhibit B.
---------


9.2 Qualification Stresses and Testing. ChipPAC is responsible for
----------------------------------
performing all qualification stresses and testing as per the
Specifications referenced in Exhibit B, except for those stresses and
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tests which Intel and ChipPAC mutually agree will be performed by
Intel. These exceptions will be documented on any new product and/or
package introduction by Intel to ChipPAC.


9.3 Traceability. ChipPAC shall demonstrate to Intel that ChipPAC's
------------
traceability system tracks each Intel Product box and unit to a
specific fab, assembly and test lot traveler, and is capable of
tracing to where each Intel Product lot was shipped and on which day.
Traceability records shall be maintained for five (5) years.


9.4 Manufacturing and Monitoring. ChipPAC shall properly manufacture,
----------------------------
monitor, test, and inspect all Intel Product and Rejects resulting
from the performance of the Services in accordance with the
specifications in Exhibits A and B. ChipPAC shall manufacture Intel
----------------
Product only at the Facilities qualified by Intel and documented in
the specifications referenced in Exhibits A and B. ChipPAC may not
----------------
move any portion of the manufacturing process to any other facility
except with the prior written approval of Intel.


9.5 Change Control. Requirements and specifications listed in Exhibits A
-------------- ----------
and B define the change control baseline. ChipPAC shall notify Intel
-----
of any proposed changes from the change control baseline at least
one hundred and twenty (120) days prior to the receipt of affected
Intel Product at Intel, per the requirements in Change Control


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Specifications listed in Exhibit B. ChipPAC shall provide Intel with
...